Very good sample NiosII UART

1, Non Interrupt


#include “unistd.h”

#include “system.h”

#include “alt_types.h”

#include “altera_avalon_uart_regs.h”

int main()


    printf(“Hello from Nios II\n”);

    alt_u8 txdata = 0;

    alt_u8 rxdata = 0;







       txdata = rxdata;






    return 0;






#include “unistd.h”

#include “system.h”

#include “alt_types.h”

#include “altera_avalon_uart_regs.h”

#include “sys\alt_irq.h”

static alt_u8txdata = 0;

static alt_u8rxdata = 0;


static void uart_isr(void * context,alt_u32 id)



    txdata = rxdata;






void uart_init()







int main()


    printf(“Please Start!\n”);





    return 0;




The method used to create a .jic file with a Nios® II hardware and software image is as follows.


1.      Create a flash file for the hardware and software image
sof2flash –input=<hwimage>.sof –output=hwimage.flash –epcs –verbose
elf2flash –input=<elf file>.elf –output=swimage.flash –epcs –after=hwimage.flash –verbose

Note: When creating the software flash image, there is no need to add a boot srec (this is located in the EPCS Controller), the –after option ensures the software image starts immediately after the hardware image.

2.      Convert the flash images into Hex files

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex
nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex

3.      When creating your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and both hex files with absolute addressing option selected.

Note: You do not need to add the .sof file to the jic image.  This is because you created a hardware hex image.  Using the hardware hex image ensures the software hex image is at the proper offset in the EPCS



Flash EPCS64 system

The error1 during flashing into EPCS using FPGA board, could not find the epcs register.

  1. This problem comes from EPCS flash controller had its RESET connected to the main Clk_Reset , but not to the JTAG_Reset : so i rebuilt in QSys after having connected the EPCS controller to the JTAG_Reset of NiosII
  2. In my project, I use Qsys> system >Great Global Reset Network to assent the EPCS and other NiosII componts.
  3. The SDRAM S1 port, should connect to both data_master and Instrument_master

In Nios II, when we flashing the EPCS, “No EPCS layout data”

This is because there is no EPCS layout information in the system, we should let the NIOS know the EPCS layout setup.

[EPCS-202011] # EPCS1N (lead-free)
sector_size = 32768
sector_count = 4
[EPCS-202013] # EPCS4N (lead-free)
sector_size = 65536
sector_count = 8
[EPCS-202015] #
EPCS16N (lead-free)
sector_size = 65536
sector_count = 32

[EPCS-010216] #EPCS64N(lead-free)
sector_size = 65536
sector_count = 128

[EPCS-202017] # EPCS64N (lead-free)
sector_size = 65536
sector_count = 128

[EPCS-012018] #EPCS128N(lead-free)
sector_size = 262144
sector_count = 64

Create a folder under the Nios2eds>bin

a document “nios2-flash-override.txt”


Always @ Verilog

This note that not all Verilog designs are synthesizable. Usually, only a very specific subset of constructs can be used in a design that is to be realized in hardware.

One important restriction that pops up is that every reg variable can only be assigned to in at most one always statement. In other words, regs have affinity to always blocks.

The following types of always blocks can generally be used.


In the former case, the * indicates that the block should be executed whenever any signal used in the block changes or, equivalently, that the block should be executed continuously. Therefore, regs that have affinity to combinatorial always blocks are implemented as signals computed from other signals using combinatorial logic, i.e. gates.

Registers that have affinity to always blocks of the latter type, on the other hand, are outputs of D flip-flops that are clocked on the rising edge of clk (falling edge if negedge is used). Inputs to the flip-flops are, again, computed with combinatorial logic from other signals.

Consider the following, somewhat contrived example.


Here, out_n is associated with the first always block, out with the second. out_n will be implemented with a single NOT gate that will drive out_n and be driven from out (note that it is a pure combinatorial logic). On the other hand, out will be driven by a flip-flop clocked from clk. The input to the flip-flop will again be computed by a NOT gate from out (which is driven by the aforementioned flip-flop). Optimizing synthesizers will combine the two NOT gates and use one NOT gate and one flip-flop.

Depending on the hardware you have available, other types of constructs can be used. For example, if the flip-flops have asynchronous resets, the following construct is also synthesizable.


FPGA Generate PWM

In FPGA, we use the counter to generate the pulse. What would happen if instead of using a 25 bit counter we used an 8 bit counter? The LED would blink at 50MHz / 2^8 = 195,313 Hz or 195,313 times per second. There is no way our eyes are fast enough to see it blink that fast. Since we can’t see it blink what would it look like? It would not look like a whole lot, it would just appear to always be on! However, the interesting part is that since it is only on for half of the time our eye averages the light and the LED appears to be dimmer than if it was on the entire time!

I recommend you try modifying the code form that tutorial to have one LED blinking from an 8 bit counter and another LED always on so you can see the difference.

How does PWM play into all of this? As you may have guessed, by varying the duty cycle of the signal we can effectively control the brightness of the LED! With a 0% duty cycle the LED is off, with a 100% duty cycle the LED is full brightness, and by controlling the duty cycles we can reach any point in between.

When we were blinking the LED we used a simplification because we always wanted a 50% duty cycle. Instead of saying the LED should be on when the counter is greater than half its max value, we simply used the most significant bit. However, in the case where we want to create a signal with an arbitrary duty cycle we need to be able to control the value we are comparing the counter to.

Here is an example where we want to create the same 33% duty cycle signal shown before.

You can see that by simply raising the value of Compare to 2/3 of Max our duty cycle became 66%!

To implement this in Verilog is pretty simple and only requires a few modifications to the blinker code.

Let’s put this all together in a project. Create a new source file called PWM.v and add the contents of the code above.



This code has something new, the parameter. Parameters are constants that are used to configure the behavior of a module when your code is synthesized. These are useful for making generic modules that can be reused.

Parameters are declared before the IO ports by using the #( … ) syntax. You can list as many parameters as you like by separating them with commas. If you assign a parameter a value, like we did in this example, then that is the default value and will be used if a value isn’t specified when the module is instantiated.

Instantiating the module

Just like before, since we added a new module, we need to instantiate it in the general file.

For this example we are going to instantiate 8 PWM modules and give each one a different constant compare value. That way we should get each of the LEDs to be at a different brightness.



For this example we set CTR_LEN to be 3 because we only need 8 different brightness values. For whatever reason, when you instantiate the module the parameters come before the name of the instance.

Go ahead and synthesize the code in ISE and load it onto your Mojo. You should see the top LED is fully on and each one under it is slightly dimmer.



SoCKit Part I – Blinking LEDs

Creating the Project

Now that you’ve created the project, you can set up the top-level file and assign the pins you need to it. In Quartus, create a Verilog file by clicking “File” -> “New” -> “Verilog HDL file”. Save the file with the same name as your project (so if you called your project “sockit_test”, save it as “sockit_test.v”. I recommend putting your HDL files in a separate subdirectory in your project folder called “rtl”.

Put the following Verilog code in “sockit_test.v”.

If you’re not familiar with Verilog, a “module” is a hardware block. In this code, we are simply specifying what the inputs and outputs of the block are. For the top-level module, the inputs and outputs are the pins of the FPGA. For our example, we only need the 4 push button keys, 4 LEDs, and the 50 MHz clock. You can assign the pins on the FPGA to your inputs and outputs by going to “Assignments” -> “Pin Planner” and entering in the following assignments.





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