Creating the Project
Now that you’ve created the project, you can set up the top-level file and assign the pins you need to it. In Quartus, create a Verilog file by clicking “File” -> “New” -> “Verilog HDL file”. Save the file with the same name as your project (so if you called your project “sockit_test”, save it as “sockit_test.v”. I recommend putting your HDL files in a separate subdirectory in your project folder called “rtl”.
Put the following Verilog code in “sockit_test.v”.
module sockit_test (
input [3:0] KEY,
output [3:0] LED
If you’re not familiar with Verilog, a “module” is a hardware block. In this code, we are simply specifying what the inputs and outputs of the block are. For the top-level module, the inputs and outputs are the pins of the FPGA. For our example, we only need the 4 push button keys, 4 LEDs, and the 50 MHz clock. You can assign the pins on the FPGA to your inputs and outputs by going to “Assignments” -> “Pin Planner” and entering in the following assignments.