January 2015

Very good sample NiosII UART

1, Non Interrupt

#include

#include “unistd.h”

#include “system.h”

#include “alt_types.h”

#include “altera_avalon_uart_regs.h”

int main()

{

    printf(“Hello from Nios II\n”);

    alt_u8 txdata = 0;

    alt_u8 rxdata = 0;

    while(1)

    {

       //查询接收准备好信号,如果没有准备好,则等待

while(!((IORD_ALTERA_AVALON_UART_STATUS(UART_BASE)&ALTERA_AVALON_UART_STATUS_RRDY_MSK)));

       //接收准备好,读取UART接收数据

       rxdata = IORD_ALTERA_AVALON_UART_RXDATA(UART_BASE);

       txdata = rxdata;

       //查询发送准备好信号,如果没有准备好,则等待

while(!((IORD_ALTERA_AVALON_UART_STATUS(UART_BASE)&ALTERA_AVALON_UART_STATUS_TRDY_MSK)));

       //发送准备好,发送txdata

       IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,txdata);

    }

    return 0;

}

2、中断方式

//中断方式

#include

#include

#include “unistd.h”

#include “system.h”

#include “alt_types.h”

#include “altera_avalon_uart_regs.h”

#include “sys\alt_irq.h”

static alt_u8txdata = 0;

static alt_u8rxdata = 0;

//UART中断服务函数

static void uart_isr(void * context,alt_u32 id)

{

    rxdata = IORD_ALTERA_AVALON_UART_RXDATA(UART_BASE);

    txdata = rxdata;

    //查询发送准备好信号,如果没有准备好,则等待

while(!((IORD_ALTERA_AVALON_UART_STATUS(UART_BASE)&ALTERA_AVALON_UART_STATUS_TRDY_MSK)));

    //发送准备好,发送txdata

    IOWR_ALTERA_AVALON_UART_TXDATA(UART_BASE,txdata);

}

void uart_init()

{

    //清除状态寄存器

    IOWR_ALTERA_AVALON_UART_STATUS(UART_BASE,0);

    //使能接受准备好中断

    IOWR_ALTERA_AVALON_UART_CONTROL(UART_BASE,0X80);

}

int main()

{

    printf(“Please Start!\n”);

    //注册UART中断服务函数

    alt_irq_register(UART_IRQ,NULL,uart_isr);

    uart_init();

    while(1){}

    return 0;

}

 

Link

The method used to create a .jic file with a Nios® II hardware and software image is as follows.

 

1.      Create a flash file for the hardware and software image
sof2flash –input=<hwimage>.sof –output=hwimage.flash –epcs –verbose
elf2flash –input=<elf file>.elf –output=swimage.flash –epcs –after=hwimage.flash –verbose

Note: When creating the software flash image, there is no need to add a boot srec (this is located in the EPCS Controller), the –after option ensures the software image starts immediately after the hardware image.

2.      Convert the flash images into Hex files

nios2-elf-objcopy -I srec -O ihex hwimage.flash  hwimage.hex
nios2-elf-objcopy -I srec -O ihex swimage.flash  swimage.hex

3.      When creating your jic file using Quartus® II Convert Programming File tool, add the Flash Loader and both hex files with absolute addressing option selected.

Note: You do not need to add the .sof file to the jic image.  This is because you created a hardware hex image.  Using the hardware hex image ensures the software hex image is at the proper offset in the EPCS

link

link2

Flash EPCS64 system

The error1 during flashing into EPCS using FPGA board, could not find the epcs register.

  1. This problem comes from EPCS flash controller had its RESET connected to the main Clk_Reset , but not to the JTAG_Reset : so i rebuilt in QSys after having connected the EPCS controller to the JTAG_Reset of NiosII
  2. In my project, I use Qsys> system >Great Global Reset Network to assent the EPCS and other NiosII componts.
  3. The SDRAM S1 port, should connect to both data_master and Instrument_master

In Nios II, when we flashing the EPCS, “No EPCS layout data”

This is because there is no EPCS layout information in the system, we should let the NIOS know the EPCS layout setup.

[EPCS-202011] # EPCS1N (lead-free)
sector_size = 32768
sector_count = 4
[EPCS-202013] # EPCS4N (lead-free)
sector_size = 65536
sector_count = 8
[EPCS-202015] #
EPCS16N (lead-free)
sector_size = 65536
sector_count = 32

[EPCS-010216] #EPCS64N(lead-free)
sector_size = 65536
sector_count = 128

[EPCS-202017] # EPCS64N (lead-free)
sector_size = 65536
sector_count = 128

[EPCS-012018] #EPCS128N(lead-free)
sector_size = 262144
sector_count = 64

Create a folder under the Nios2eds>bin

a document “nios2-flash-override.txt”

 

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